A switching power source system including a switching element connected to a primary-side circuit and a control IC controlling the switching element is known as a switching power source system that converts a commercial power source to a DC power source for an electric/electronics apparatus. FIG. 1 in page 1577 of Non-Patent Document 1 discloses an example in which such a switching power source system is realized by a combination of a vertical power MOSFET and a control circuit.
Patent Document 1 discloses an arrangement that realizes such a switching power source system with a monolithic IC or one chip by embedding a switching transistor composed of a lateral power MOSFET in a control circuit.
Moreover, in an arrangement disclosed, a control IC and a switching transistor are separately packaged, in a conventional switching power source system. (Non-Patent Document 2)
FIG. 5 of Patent Document 2 discloses an arrangement in which two chips including a control IC chip and a switching transistor chip are arranged in one package. However, because a switching transistor is a vertical transistor in general, a die bonding area becomes a drain (collector). This causes a large potential difference between a potential (generally, GND) of a backside of the control IC and a potential of the drain (collector) of the vertical transistor, in terms of a circuit. Accordingly, it is necessary to insulate the backside of the control IC chip from the die bonding area of the switching transistor. For the insulation, an insulating sheet is provided on the backside of the control IC when the control IC is die-bonded.
Alternately, in a known arrangement, an island of a lead frame is divided, for the purpose of realizing insulation between the backside of the control IC chip and the die bonding area of the switching transistor. The control IC chip is die-bonded on one island. On the other island, the switching transistor is die-bonded. (FIG. 1 and FIG. 2 of Patent Document 2)
FIGS. 1 and 2 of Patent Document 3 disclose an arrangement in which a vertical power MOSFET is fabricated as a discrete MOSFET.    [Patent Document 1]    U.S. Pat. No. 5,023,678, FIG. 5    [Patent Document 2]    Japanese Unexamined Utility Model Publication No. 197358/1988 (Jituskaishou 63-197358), FIGS. 1, 2, and 5    [Patent Document 3]    U.S. Pat. No. 4,376,286, FIGS. 1 and 2    [Non-Patent Document 1]    IEEE Transactions on Electron Devices, Vol. 38, No. 7, July 1991: p. 1577, FIG. 1    [Non-Patent Document 2]    CQ Publishing Co. Ltd., Transistor Technology Special No. 28, All about Latest Power Circuit Design Technologies, p. 106, FIG. 8, issued on Jul. 1, 1991
In an arrangement disclosed in Non-Patent Document 1, a vertical power MOSFET is adopted as a switching transistor. The vertical power MOSFET structurally has a junction field effect transistor (hereinafter, referred to as J-FET) between adjacent bodies. A parasitic J-FET increases an on-resistance of the vertical power MOSFET. In order to decrease the parasitic resistance of the J-FET, a distance equal to or more than 20 μm is necessary between adjacent vertical power MOSFETs. As a result, a gate electrode becomes long. Consequently, a gate capacitance of the switching transistor increases.
For the reason mentioned above, a gate capacitance of the switching transistor increases. Consequently, a large output current from a control circuit becomes necessary for driving the switching transistor. This leads to an increase in a size of an output transistor of the control circuit. As a result, a chip size increases. This causes cost increase. Moreover, because a gate capacitance of the switching transistor increases, the switching transistor cannot deal with high-speed switching.
In an arrangement disclosed in Patent Document 1, a control IC can be fabricated at a low cost by using a fine process that is a low voltage process, because the chip size can be decreased by the process. Meanwhile, a switching transistor requires a high voltage process having a large design rule. Formation of these two devices in one chip requires a process that realizes performances of the both devices. This results in a quite expensive processing cost. As to the number of masks, for example, in a case where the devices are separately fabricated, 13 masks for the control IC and 9 masks for the switching transistor are necessary. However, 17 masks are necessary for fabricating the devices in one chip, and an entire area of the chip needs to be fabricated with this number of masks. This means that both the control IC and the switching transistor are fabricated on the same chip with 17 masks. Therefore, this clearly leads to a cost increase for the one-chip arrangement compared with a two-chip arrangement.
According to an arrangement disclosed in Non-Patent Document 2, each of a control IC and a switching transistor is individually molded in a mold assembly. As a result, a cost becomes high. Moreover, reduction in size becomes impossible.
Furthermore, because wiring provided between the control IC and the switching transistor is long, an inductor component of this wiring causes distortion in a switching transistor drive signal waveform generated by the control IC. As a result, the switching transistor does not function as intended in designing. Consequently, a conversion efficiency of an entire power source circuit deteriorates.
In addition, because of the long wiring between the control IC and the switching transistor, the power source circuit tends to be influenced by noise from other circuit. This causes distortion in a switching transistor drive signal waveform generated by the control IC. As a result, the switching transistor does not function as intended in designing. Consequently, a conversion efficiency of the entire power source circuit deteriorates.
Because of the long wiring between the control IC and the switching transistor, an operation of a capacitance between this wiring and GND requires supply of a current for charge/discharge of the capacitance between the wiring and the GND at the time when the control IC generates a switching transistor drive signal. Accordingly, the control IC needs to have driving ability. This leads to an increase in a consuming power of the control IC and an increase in a chip size.
In an arrangement disclosed in FIG. 5 of Patent Document 2, an insulating sheet is expensive. Moreover, because a control IC chip is capacitively coupled with a lead frame having a voltage amplitude equal to or more than 100V via an insulating sheet, a circuit of the control IC may malfunction.
In an arrangement disclosed by FIGS. 1 and 2 of Patent Document 2, an island to which the control IC chip is die-bonded is GND in terms of a circuit. On the other hand, an island to which a switching transistor chip is die-bonded has a voltage amplitude equal to or more than 100V. Consequently, capacitive coupling between these islands may cause malfunction of a circuit of the control IC. For the purpose of preventing the malfunction, it is necessary to decrease a capacitance between the islands. This requires equal to or more than a predetermined spacing. However, this conventional technique does not teach nor suggest the spacing.
The switching transistor consumes a large amount of power and generates a large amount of heat. However, a rise in a temperature of the control IC should be prevented for stable operation of the control IC. An effect of this conventional technique makes it difficult to transmit heat generated by the switching transistor to the control IC. However, the conventional technique does not teach nor suggest a spacing between the islands which spacing is necessary to obtain the effect.
Moreover, in a case where solution is required for dissipating heat of the switching transistor in a high-capacity power source, it is necessary to expose, from a backside of a package, only the island on which the switching transistor is mounted and connect the island to an external heat dissipation plate. This complicates a frame structure in the extreme and leads to cost increase.
The object of the present invention is to provide an output control device capable of reducing a chip size and realizing a low cost.